Clock pulse generating circuit
US4974081A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 1990 |
| Grant date | Nov 27, 1990 |
| Priority date | — |
| Expiry date | Mar 13, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/937
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A clock pulse generating circuit is provided which is capable of generating a stabilized clock pulse without being effected by disturbance due to the vertical equalizer pulse. The clock pulse generating circuit includes a PLL circuit for generating a clock pulse which is phase-synchronized with an input signal. The circuit further includes a synchronizing circuit for generating a window pulse synchronized with the horizontal synchronizing signal by being operated with a clock pulse generated by the PLL circuit as a reference. The synchronization condition is judged with respect to the composite synchronizing signal and a gate circuit which permits passage of the composite synchronizing signal only during the period of existence of the window signal. Accordingly, the signal is constructed so as to select the composite synchronizing signal before passage through the gate in an asynchronous condition of the synchronizing circuit. Similarly, the composite synchronizing signal is passed after passage through the gate in a synchronous condition, the composite synchronizing signal being used as the input to the PLL circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.