Bus arbiter with equitable priority scheme
US4974148A · kind A · utility
21Cited by
12References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 6, 1987 |
| Grant date | Nov 27, 1990 |
| Priority date | — |
| Expiry date | Jul 6, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus arbiter for a multi-processor computer provides fair access by dynamically adjusting a base variable of a counter which is determined from a processor number of a previously access-requesting processor having the highest processor number. The counter then varies priority between a minimum processor number, such as zero, and the base variable of the counter. The priority signal from the counter and the current access-requesting processors are then provided to a memory device. The memory device is used to determine which current access-requesting processor is permitted to access the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.