Generalized digital multiplier and digital filter using said multiplier
US4974186A · kind A · utility
5Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 24, 1989 |
| Grant date | Nov 27, 1990 |
| Priority date | — |
| Expiry date | Jan 24, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5443
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The multiplier according to the invention comprises N shift registers (RD.sub.O, . . . , RD.sub.N-1) containing the words x.sub.i on B bits, N conditional adders (AdC.sub.O, . . . , AdC.sub.N-1) each adding to the partial sum which they receive a constant coefficient (a.sub.1), conditional on the value of the bit (x.sub.i,j) which they receive from the associated register (RD.sub.1) and an adder accumulator (AdAc). The digital filter using such a multiplier also comprises a parallel word input register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.