Josephson memory and read/write circuit
US4974205A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 23, 1989 |
| Grant date | Nov 27, 1990 |
| Priority date | — |
| Expiry date | Oct 23, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/44
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Josephson memory circuit driven by first, second and third clock signals includes a write circuit which holds data as a circulating current circulating in a superconducting closed loop including a Josephson junction. The data to be held is supplied thereto through a data line with timing of the third clock signal. A first OR circuit is supplied with a bias from a read bias line with timing of the second clock signal and supplied with the circulating current. The first OR circuit has a Josephson junction which is switched to a finite resistance state by the circulating current. A second OR circuit is supplied as a bias with output data form the first OR circuit with timing of the second clock signal and supplied with a read address signal from a read address line with timing of the first clock signal. The second OR circuit has a Josephson junction which is switched to a finite resistance state by the read address signal. A third OR circuit is supplied with a bias from a read line with timing of the second clock signal and supplied with output data from the second OR circuit. The third OR circuit has a Josephsoh junction which is switched to a finite resistance state by the output …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.