Data receiver interface circuit
US4974225A · kind A · utility
8Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 1989 |
| Grant date | Nov 27, 1990 |
| Priority date | — |
| Expiry date | Sep 14, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0626
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A data receiver interface circuit is provided with a circuit for accepting correctly framed data. The plurality of data bits sandwiched between a pair of frame pulses is temporarily stored while the number of clock cycles occurring between the frame pulses is determined to be a valid number. The data is accepted by the receiver if the number of clock cycles occurring between the pair of successive frame pulses is a valid number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.