Scannable register/latch circuit
US4975595A · kind A · utility
62Cited by
8References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 20, 1988 |
| Grant date | Dec 4, 1990 |
| Priority date | — |
| Expiry date | Jul 20, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/289
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit is described for functioning as a transparent latch, a latch where the data is determined by the state of a data signal at the time a signal changes state, a D-type flip-flop, and a scan path element. The mode of operation of the circuit is determined by the condition of respective ones of a set of control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.