Integrated circuit and method for testing the integrated circuit
US4975641A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1989 |
| Grant date | Dec 4, 1990 |
| Priority date | — |
| Expiry date | Apr 21, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31701
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit which can be operated in a test mode includes a test input terminal for instructing the switching between an actual use mode and a test mode, a plurality of input terminals, an AND gate for performing logic operations on the input signals from the input terminals, a plurality of flip-flops for storing each of the input signals from the remaining plurality of input terminals by using the outpout of the AND gate as a timing signal, a decoder for producing a test mode designating signal to select one test mode from a plurality of test modes in response to each of the outputs of the flip-flops, and a control circuit for operating a processing circuit in the test mode designated by the test mode designating signal in response to the test mode setting signal from the test input and the test mode designating signal from the decoder. The configuration of this circuit permits the testing of the signals from the output terminals of the integrated circuit without excessively increasing the number of input terminals necessary for the test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.