High speed communication processing system
US4975695A · kind A · utility
35Cited by
7References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1987 |
| Grant date | Dec 4, 1990 |
| Priority date | — |
| Expiry date | Oct 1, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/0407
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A communications node for handling circuit and packet switching and capable of expansion to include multiple switching matrices, multiple network processors and multiple packet processors is disclosed. Each switch matrix has multipile I/O ports and communications with user interfaces, network interfaces and other system components via bidirectional data links. At least one switch matrix is connected via a bidirectional data link to a packet processor and a network processor. All processors are interconnected via a computer bus. Switch matrices are connected to each other either by a backplane bus or via bidirectional data links.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.