Duplex data processing system with programmable bus configuration
US4975838A · kind A · utility
39Cited by
11References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 9, 1987 |
| Grant date | Dec 4, 1990 |
| Priority date | — |
| Expiry date | Apr 9, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A duplex data processing system includes two processors each provided with a bus connecting unit which disconnects the associated CPU bus from the cross connection bus in a separate mode or connects the CPU bus to the cross connection bus in a duplex mode. The system operates with a logically unified CPU bus through the connection of the internal CPU buses by the two bus connecting units in both processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.