Parallel array processor with interconnected functions for image processing
US4975843A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1988 |
| Grant date | Dec 4, 1990 |
| Priority date | — |
| Expiry date | Nov 25, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array processor has been designed in a highly paralleled fashion thereby allowing extremely fast movement of data. Two 32-bit words come out of an internal data memory device. This data is fed into a register file. On the same clock cycle, three 32-bit results are coming out of an arithmetic unit. Those results feed back into the register file. Therefore, on a single clock cycle, five separate pieces of data are going into the register file. In the same clock cycle, other data coming out of the outputs of the register file feed data into two separate floating arithmetic adders and one floating arithmetic multiplier. The design of the present embodiment allows a constant flow of data to be supplied to the arithmetic unit thereby using the arithmetic unit to its maximum functioning ability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.