Static semiconductor memory with improved write recovery and column address circuitry
US4975877A · kind A · utility
34Cited by
12References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 20, 1988 |
| Grant date | Dec 4, 1990 |
| Priority date | — |
| Expiry date | Oct 20, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory (SRAM) having a reduced access time for reading and reduced probability of inadvertent writing operations. Switching circuits (multiplexers) that are used to connect column bit lines with reading and writing circuits of the memory are divided into separate circuits for use during read and write operations. A recovery pulse is applied only to bit lines of a column just written to by use of the driving circuits through the same column line switching circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.