Clock recovery apparatus
US4975929A · kind A · utility
11Cited by
15References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 11, 1989 |
| Grant date | Dec 4, 1990 |
| Priority date | — |
| Expiry date | Sep 11, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/044
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital phase acquisition circuit includes logic for detecting an edge of incoming data and a plurality of candidate clock phases, the circuitry further including logic for determining when the data undergoes a phase transition and at least one candidate phase which undergoes a digitally equivalent transition close in time to the data transition so as to enable the candidate phase to be used for a clock for recovering information representative of the data. The circuit allows clock to be recovered within 1 bit time of a predetermined data transition occurring, thus allowing preambles of 1 bit to be utilized in data packets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.