High speed programmable divider
US4975931A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 19, 1988 |
| Grant date | Dec 4, 1990 |
| Priority date | — |
| Expiry date | Dec 19, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable counter or frequency divider includes the combination of a fixed modulus prescaler (110) and a programmable divider (120, 130, 140, 150, 160) in which the prescaler provides more than a single clock phase to the programmable divider and the programmable divider utilizes the multiple clock phases to allow operation in a true fractional-integer mode. The overall combination of the prescaler and programmable divider functions as a programmable divider for which the minimum increment in the overall divider modulus is less than the prescaler modulus, but the maximum clock frequency usable is the maximum clock frequency of the prescaler.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.