Combined deemphasis circuit and noise blanker
US4975953A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 1989 |
| Grant date | Dec 4, 1990 |
| Priority date | — |
| Expiry date | Jan 13, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G3/345
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An FM stereo radio circuit has an ultrasonic noise detector and an amplitude noise detector each for detecting impulse noise by developing an average noise signal and comparing the average noise signal with an attenuated value of the instantaneous noise signal to generate a noise flag. A dual mode circuit normally operates as a low pass filter for a deemphasis function and is switched by the noise flag to operate as a sample and hold circuit which blanks the noise pulse. The dual mode circuit uses a switched capacitance design and is driven by clock signals to serve as a filter. The clock signals are stopped by the noise flag to effect the sample and hold function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.