Monolithic pressure sensitive integrated circuit
US4977101A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 1989 |
| Grant date | Dec 11, 1990 |
| Priority date | — |
| Expiry date | Aug 21, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/924
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A monolithic pressure sensitive silicon integrated circuit is formed by first providing a localized etch-stop layer on one surface of the silicon chip, then growing successive epitaxial layers of opposite conductivity types over this surface. In the upper of the two layers, there is formed a bridge of four piezoresistors overlying the periphery of the etch-stop layer and the conditioning circuitry for amplifying the output of the bridge including both lateral and vertical junction transistors. The back surface of the chip is etched anisotropically to form a cavity that leaves a thin diaphragm underlying the bridge of the four piezoresistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.