High speed digital motion controller architecture
US4977494A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 1989 |
| Grant date | Dec 11, 1990 |
| Priority date | — |
| Expiry date | Feb 17, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B2219/34205
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A system bus (13) carrying multidimensional path data interfaces with a plurality of local microprocessors (24), one for each dimension, through a plurality of dual access memory structures (21), one for each local microprocessor (24). A local arbiter (35) controls access to each dual access memory structure (21), facilitating elimination of wait states in data transfers between the bus (13) and memory (21) and between the local microprocessor (24) and memory (21). The arbiter (35) is implemented using a programmable logic device state machine approach, which implements a mode of operation wherein the circuitry is armed for a transfer between a local microprocessor (24) and the dual access memory (21) and accomplishes such transfer with no wait states. The state machines and dual access memory (21) are driven by a clock which is twice as fast as that driving the local microprocessor (24) and the state machine implementation utilizes this fact to insure memory access to both the system bus (13), and the local microprocessor (24) with priority going to the local microprocessor (24).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.