Hierarchical variable die size gate array architecture
US4978633A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 1989 |
| Grant date | Dec 18, 1990 |
| Priority date | — |
| Expiry date | Aug 22, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/998
Abstract
A variable die size gate array architecture is realizable by forming in a semiconductor substrate an array of circuit devices separated from one another by a network of routing channels. Through the selective interconnection of the routing channels and the circuit devices a prescribed signal processing function may be implemented. The array of circuit devices includes gate supercells each of which is configurable to perform a respective signal processing operation, and input/output supercells each of which is configurable to effectively perform input/output interfacing between the gate supercells and signal terminals external to the array. The gate supercells and the input/output supercells are intermingled with one another in the array in accordance with a prescribed two-dimensional distribution pattern. Prescribed ones of the gate supercells and input/output supercells within at least one prescribed portion of the array are interconnected to effectively form an integrated circuit architecture capable of implementing the prescribed signal processing function. This portion is then separated from the wafer, and the integrated circuit architecture resident in the separated portion of…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.