Ramp circuit for control loop
US4978866A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 1988 |
| Grant date | Dec 18, 1990 |
| Priority date | — |
| Expiry date | Jul 1, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05D23/22
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A ramp circuit for a control loop which receives a signal from a controller and sends a signal to a controllable means to limit the slew rate of the controller signal. A capacitor functions as a storage means and a reset means is provided to rapidly discharge the capacitor in the event of a decrease in power to the control loop. The capacitor is charged through a diode which limits discharge in normal operation. The discharge and reset is performed by a normally reverse biased diode and series resistance connected to the controller positive supply voltage. A current limiting means is provided to charge the capacitor a lower linear rate by turning on a transistor and shunting excess current around the capacitor. An external reset is provided by an additional diode and series resistance for connection to a remote positive supply voltage or relay contact. The output is buffered by an emitter follower to limit loading by the controllable means and protection circuitry to provide immunity to induced electrical currents at the output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.