CMOS analog four-quadrant multiplier
US4978873A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 11, 1989 |
| Grant date | Dec 18, 1990 |
| Priority date | — |
| Expiry date | Oct 11, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A four-quadrant analog multiplier circuit provides an output which is protional to two voltage inputs that each represent a multiplicand. In a first embodiment, the circuit comprises a complementary pair of field effect transistors having gain constants equal in magnitude and in which the p-channel threshold voltage is larger than the n- channel threshold voltage. The gates of the transistors are coupled in common. One input is added to a bias voltage and the voltage sum is applied to the common gates. The other input and its inverse are separately applied to source/drain terminals of the two transistors, while the remaining source/drain terminals are coupled in common to provide an output node. A second embodiment of the invention is composed of two circuits as described above, where the polarities of the inputs to one pair of transistors are reversed relative to those of the second pair, and the output nodes of the individual pairs are coupled together.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.