Noise reduction output buffer
US4978905A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1989 |
| Grant date | Dec 18, 1990 |
| Priority date | — |
| Expiry date | Oct 31, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S323/907
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A circuit for compensating for MOS device response to supply voltage variations, as well as temperature and process variations, in an integrated circuit device. The compensation circuit produces a reference voltage which modulates the gate bias voltage of a MOS transistor such that the gate-to-source bias of the MOS transistor is varied to compensate for variations in the supply voltage as well as for variations in the temperature and manufacturing process. The circuit pulls up the reference voltage toward the supply voltage as the supply increases, thereby increasing the gate drive on the MOS transistor. The circuit provides compensation for both AC and DC supply variations. The MOS transistor is used to modulate the available current sinking capability in an IC device output buffer, such that as the MOS gate drive increases, the current sinking capability is reduced, thereby slowing the output state transitions as the supply increases, and reducing noise caused by supply variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.