Quasi-fair arbitration scheme with default owner speedup
US4979099A · kind A · utility
19Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1988 |
| Grant date | Dec 18, 1990 |
| Priority date | — |
| Expiry date | Oct 25, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/378
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decentralized, pipelined, synchronous bus arbitration scheme which allows almost completely fair arbitration between multiple devices competing for the use of a communication bus while allowing the device that last used the bus faster access to the bus if no other device is competing for its use. The arbitration method and apparatus according to the present invention allows all competing devices equal access to the bus, with the exception that when bus requests are posted simultaneously, the device with the higher priority will always be granted use of the bus first.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.