Communication processor for a packet-switched network
US4979100A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1988 |
| Grant date | Dec 18, 1990 |
| Priority date | — |
| Expiry date | Apr 1, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/56
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet switch receives data and processes it for assembly into packages. A bus allows communication between each of the data processing units of the switch and one or more storage units for storing the data packets. Arbitration for deciding which of the processing units will be granted access to the bus is performed by a system which selectively and alterably designates any of at least two different levels of priority of access to the bus for each of the processing units, and the relative percentages of time of access for the different priorty levels. The system assures greater access to the bus by those of the processing units having the higher level of priority. If communication is provided by two buses, the requests for access are alternated between them. The arbitration system provides selective access to the bus in any of a plurality of bus cycles including a read cycle, a write cycle and a read/modify/write cycle, and grants a request for access from a higher priority processing unit within one bus cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.