Dual microprocessor control system
US4979104A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1987 |
| Grant date | Dec 18, 1990 |
| Priority date | — |
| Expiry date | Mar 31, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/124
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor control system for use in an asynchronous data communication system and comprising a receive microprocessor and a transmit microprocessor along with a paged memory for storing channel line tables. Separate receive and transmit channel number registers control access to the paged memory. Control means is provided preferably in the form of a programmable memory for controlling the sequenching of channel numbers whereby one microprocessor is adapted to access channels in an incrementing manner while the other accesses in decrementing manner. When one microprocessor gains access to a specific line table excludes the other microprocessor from accessing that line table until the first microprocessor suspends off of that line table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.