Multi-stage wideband successive detection logarithmic amplifier
US4980584A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1988 |
| Grant date | Dec 25, 1990 |
| Priority date | — |
| Expiry date | Oct 14, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A successive detection logarithmic amplifier consists of multiple stages, with each stage containing a field-effect transistor (FET) which functions as both an amplifier and a detector. The FET, having an external gate biasing terminal, is biased to operate in its linear region as an amplifier. The gate-source junction of the FET, which is a diode, functions as the detector. When a signal exceeding a predetermined threshold is applied to the FET, the gate-source junction conducts current in the forward direction during the positive half-cycles of the input signal. During the negative half-cycles of the input signal, very little current flows through the gate-source diode junction. The time average of the forward current peaks produces a voltage across a resistor connected between the external gate bias terminal and ground. The voltages at the external gate bias terminals of each of the stages are summed to form a video output signal, a piece-wise linear voltage which is a logarithmically proportional to the input signal at the initial stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.