Folded bitline dynamic ram with reduced shared supply voltages
US4980862A · kind A · utility
17Cited by
1References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 8, 1988 |
| Grant date | Dec 25, 1990 |
| Priority date | — |
| Expiry date | Nov 8, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A folded bitline dynamic RAM circuit with reduced shared supply voltages comprised of circuitry for applying full logic high and low supply voltages to respective bitlines during successive active cycles of the RAM circuit, and circuitry for applying reduced supply voltages to the bitlines during successive precharge cycles. By applying reduced supply voltages to the bitlines during the precharge cycles voltage stress on cell access transistors and sense amplifiers of the RAM circuit are reduced. The time required to share the charge residing on the bitline halves at the start of the active cycle is also reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.