Subsampling time-domain digital filter using sparsely clocked output latch
US4982353A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1989 |
| Grant date | Jan 1, 1991 |
| Priority date | — |
| Expiry date | Sep 28, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The plural-phase clocking signal used in a subsampling time-domain digital filter is partially blanked to generate a sparse clocking signal for a clocked data latch that decimates the output signal from the digital filter, to supply it at a subsampling rate as compared to the sampling rate of input signal to the filter. The blanking signal is generated from a counter that counts occurrences of pulses in the plural-phase clocking signal, which counter comprises a ripple-carry adder and another clocked data latch arranged to accumulate successive unit values. This procedure guarantees correct timing of clocking signal for the output latch vis-a-vis the plural-phase clocking signal used in the preceding time-domain digital filter despite the time taken for carry ripplethrough in the counter adder. Digital hardware is conserved by blanking only one phase of the plural-phase clocking signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.