Memory subsystem
US4982360A · kind A · utility
25Cited by
7References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 22, 1983 |
| Grant date | Jan 1, 1991 |
| Priority date | — |
| Expiry date | Sep 22, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory subsystem including a read-only memory (ROM), a random access read/write memory (RAM) and a selection system for selecting the output of one of the memories for use by downstream circuitry. The selection of the output is based on input address signals so that the contents of the RAM can substitute for the contents of selected locations in the ROM. If a substitution is to be made, an entry is made in a content addressable memory, which stores addresses for which the RAM output is to be substituted for ROM output. A test system is provided to verify the contents of the content addressable memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.