Process for fabricating heterojunction bipolar transistors
US4983532A · kind A · utility
11Cited by
2References
14Claims
0Family size
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Key dates
| Filing date | Dec 20, 1988 |
| Grant date | Jan 8, 1991 |
| Priority date | — |
| Expiry date | Dec 20, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/10
Abstract
Microfabrication and large scale integration of a device can be realized by using a planar heterojunction bipolar transistor formed by a process comprising successively growing semiconductor layers serving as a subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that at least one of the emitter junction and collector junction is a heterojunction, wherein a collector drawing-out metal layer is formed by the selective CVD method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.