Memory block address determination circuit
US4984213A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 1989 |
| Grant date | Jan 8, 1991 |
| Priority date | — |
| Expiry date | Feb 21, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0676
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An adder and a comparator form portions of a modular memory address block determination circuit. The starting address of the first block and the enable signal of the first block are added to produce the starting address of the second block. This procedure is repeated for each block. The determined starting address for each block is compared with the requested memory address and, unless the block is utilized or disabled, if equal a signal indicates the match. The circuit is used on a circuit board which emulates three conventionally separate memory circuit boards. The registers for each emulated board are provided and appropriate bus signals are developed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.