Method of manufacturing a lateral transistor
US4985367A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 11, 1989 |
| Grant date | Jan 15, 1991 |
| Priority date | — |
| Expiry date | Jul 11, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a lateral transistor which comprises the steps of forming N type semiconductor silicon layer on P type semiconductor substrate, depositing base region on part of the semiconductor silicon layer, forming field oxide layer bearing an opening on the base region, forming thin insulation layer on that part of the semiconductor body which is exposed by the opening, forming an annular pattern on the thin insulation layer, implanting a P type impurity in the base region, thereby providing an emitter region and collector region in the self-aligned fashion with respect to the annular pattern, retaining the annular pattern, and depositing insulation layer on the resultant structure, boring an emitter contact hole having a smaller diameter than the outer diameter of the annular pattern, and forming emitter contact hole in the self-aligned fashion with respect to the annular pattern, and forming emitter electrode in contact with the emitter region through the contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.