BiCMOS logic circuit having a rapid output voltage falling-down property
US4985645A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 1989 |
| Grant date | Jan 15, 1991 |
| Priority date | — |
| Expiry date | Sep 26, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09448
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A BiCMOS logic circuit includes a MOS logic circuit connected between a high voltage supply line and a low voltage supply line and having an input connected to an input terminal, and an output circuit composed of first and second bipolar transistors connected in series between the high and low voltage supply lines. The first bipolar transistor has a base connected to an output of the MOS logic circuit, and a connection node of the first and second bipolar transistors is connected to an output terminal. In addition, a base current supplying circuit having first and second MOS transistors is connected in series between the first voltage supply line and a base of the second bipolar transistor. The first MOS transistor has a gate connected to the output of the MOS logic circuit, and the second MOS transistor has a gate connected to the input terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.