Interprocessor bus switching system for simultaneous communication in plural bus parallel processing system
US4985830A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 1988 |
| Grant date | Jan 15, 1991 |
| Priority date | — |
| Expiry date | Sep 27, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus switching apparatus and method for multiple processor computer systems comprises a plurality of bus switches interconnected by branch buses. Each processor or other module of the system is connected to a spigot of a bus switch. Each bus switch also serves as part of a backplane of a modular crate hardware package. A processor initiates communication with another processor by identifying that other processor. The bus switch to which the initiating processor is connected identifies and secures, if possible, a path to that other processor, either directly or via one or more other bus switches which operate similarly. If a particular desired path through a given bus switch is not available to be used, an alternate path is considered, identified and secured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.