Process for improved planarization of the passivation layers for semiconductor devices
US4986878A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 1988 |
| Grant date | Jan 22, 1991 |
| Priority date | — |
| Expiry date | Jul 19, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/958
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an integrated circuit having a multilayer structure where the method includes the steps of depositing a thin layer of low temperature oxide (LTO) on top of conductors and then spinning and curing a thin layer of spin-on-glass to planarize the surface of the device. This structure is then plasma etched to remove the spin-on-glass and a portion of the LTO at approximately the same rate. The structure is then dipped in a mild potassium hydroxide solution to completely remove the SOG material, even from the crevices and gaps which are present on the surface. This enables the device to be manufactured free of any organic substances from the SOG in the body of the structure. A passivation layer can now be deposited to protect the underlying circuitry from ionic contamination, water vapor penetration and handling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.