High-speed CMOS buffer with controlled slew rate
US4987324A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1987 |
| Grant date | Jan 22, 1991 |
| Priority date | — |
| Expiry date | Aug 27, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09429
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-speed CMOS output buffer reduces transient current surges and provides high output DC drive. The buffer includes a first and a second CMOS inverter connected in parallel. Each of the two CMOS inverters includes an N channel and a P channel transistor. The gates of the transistors in the first inverter are controlled by a first control inverter having a first selected switching threshold voltage. The gate of the P channel transistor in the second inverter is controlled by a second control inverter having a switching threshold voltage higher than that of the first control inverter. The gate of the N channel transistor in the second inverter is controlled by a third control inverter having a switching threshold voltage lower than that of the first control inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.