Semiconductor integrated circuit device having an improved common wiring arrangement
US4987326A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1989 |
| Grant date | Jan 22, 1991 |
| Priority date | — |
| Expiry date | Apr 28, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a gate array integrated circuit including a plurality of logic gate circuits having a wired-OR form, or the like, a first common combined wiring is provided for connecting the output side in such a manner that the output terminal of each logic gate circuit and a branch node corresponding thereto are in the proximity of one another. A terminal resistor is interposed between a first end of the first common combined wiring and a power source voltage or ground potential of the circuit, and the second end of the first common combined wiring is coupled to a second common combined wiring connecting the input terminals of the logic gate circuits on the input side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.