Operational amplifier circuit
US4987379A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 24, 1989 |
| Grant date | Jan 22, 1991 |
| Priority date | — |
| Expiry date | Aug 24, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45496
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An operational amplifier circuit comprises a differential input stage (22) and an output transistor (N3) driven by an output (24) of the differential input stage. Means (N4, P3, P5) for generating a bias current for the differential input stage are constructed so that in operation the bias current is in a predetermined proportion to the current flowing in the output transistor (N3) and is substantially independent of the impedance (Z) of any load driven by the output transistor, thereby eliminating a systematic offset error. The means for generating the bias current may include a further transistor (N4) driven by the output of the differential input stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.