Semiconductor memory device having a plurality of access ports
US4987559A · kind A · utility
43Cited by
1References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 1989 |
| Grant date | Jan 22, 1991 |
| Priority date | — |
| Expiry date | Mar 6, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1075
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved semiconductor memory device in which serial read operations and serial write operations can be performed simultaneously is disclosed. The memory device comprises a memory array of memory cells, a random access port for accessing a desired one of memory cell in the array, a serial read circuit for sequentially reading data from the selected row one by one and a serial write circuit for operatively writing data sequentially applied to the selected row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.