Method and circuit for generating dependent clock signals
US4988892A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 2, 1989 |
| Grant date | Jan 29, 1991 |
| Priority date | — |
| Expiry date | Jun 2, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and circuit generate a dependent clock signal from a master clock signal with minimal skew of the dependent clock signal with respect to the master clock signal and inverting it to create a second master clock signal that is one hundred eighty degrees out of phase with the first master clock signal. The second master clock signal is used to drive a flip flop type circuit so that the flip flop circuit changes states when the first master clock signal is at a "zero" level and the second master clock signal is at a "one " level. The output of the flip flop circuit is enabled using the first master clock signal. Connected to the output of the tri-state driver is a repeater circuit of the type having an output that remains the same as the input until the input level is changed. The resulting dependent clock signal has a minimal skew with respect to the first master clock signal because the output of the flip flop circuit has become stable by the time the tri-state driver is enabled by the first master clock signal. Thus, the skew line is limited to the delay time of the tri-state driver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.