Internal timing circuit for a CMOS programmable logic array

US4990801A · kind A · utility

Assignee

• Deutsche ITT Industries, GmbH · DE

Inventors

• Knut Caesar · Gundelfingen, DE
• Helmut Haeringer · Niederwinden, DE

Key dates

• Filing date: Jun 15, 1989
• Grant date: Feb 5, 1991
• Expiry date: Jun 15, 2009

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/1772
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A programmable logic array implemented with complementary insulated-gate field effect transistor technology and formed on a substrate employing a standard AND-OR structure and two non-overlapping clock phases uses diffused capacitors in a dummy row to model the worst case evaluation time of minterms in the AND plane, and a NOR gate, responsive to the dummy row, for enabling the OR plane to sum the minterms generated by the AND plane.