Method and system for extending address space for vector processing
US4991083A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Aug 4, 1988 |
| Grant date | Feb 5, 1991 |
| Priority date | — |
| Expiry date | Aug 4, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for extending an address space for a vector processor including a vector processing unit and a scalar processing unit. A main storage and an extended storage are also disclosed. An address translator is provided for each requestor within the vector processing unit. Each address translator includes registers for storing main storage addresses and extended storage addresses for the address translation, a register for storing information such as an invalid bit regarding an address space present on the main storage, a register for storing information such as a protection bit representative of an address translation enabled area, and registers for storing a reference bit and a write bit representative of the main storage reference status. The scalar processing unit includes an access controller for allowing a write/pad operation relative to the respective registers in the address translator. The vector processing unit includes a first logic circuit for temporarily suspending a main storage reference request sent from the requestor to an area not present on the main storage, a second logic circuit for releasing the suspension, and a third logic circuit for informin…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.