Dynamic random access memory with improved sensing and refreshing
US4991142A · kind A · utility
14Cited by
6References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 20, 1989 |
| Grant date | Feb 5, 1991 |
| Priority date | — |
| Expiry date | Jul 20, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention uses two pairs of cross coupled n-channel sense amplifier transistors attached between two electrically balanced halves of a bit line. Disposed between each pair of cross coupled n-channel sense amplifier transistors is only one pair of p-channel restore transistors attached between the bit line and complement bit line. Furthermore, on the bit line and complement bit line, between one pair of cross coupled n-channel sense amplifier transistors and the pair of p-channel restore transistors, are depletion type isolating transistors that further isolate halves of the bit line and complement bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.