Echo reduction circuit
US4991166A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 28, 1988 |
| Grant date | Feb 5, 1991 |
| Priority date | — |
| Expiry date | Oct 28, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M9/10
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An echo reduction circuit that may be used to reduce the returned echo in communication links with signficant delay. By making effective use of the echo-masking effect of near-simultaneous desired speech energy and the redundancy present in normal speech, the circuit makes possible wide bandwidth, non-choppy, perceived distortion-free, and perceived echo-free teleconferencing. The circuit performs a rapid time constant, semi-waveform-following partial attenuation of a preemphasized version of the returning transmit signal proportional to a calculation of the likely strength of the returned echo in relation to the strength of the local speech.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.