Method of testing n-bit programmable counters
US4991185A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 1990 |
| Grant date | Feb 5, 1991 |
| Priority date | — |
| Expiry date | Jan 3, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
This invention relates to a method of testing an n-bit programmable counter. It is desired to test the n-bit programmable counter in fewer than 2.sup.n cycles. Accordingly, a counter value output on the counter is coupled to a variable increment rate input on the counter. Each bit of the counter is reset to a binary 0 initial state. A binary 1 state is loaded into a carry-in bit of the counter and the counter is iteratively doubled, by means of the coupling between the counter value output and the variable increment rate input, until a carry-out bit of the counter assumes the binary 1 state to thereby allow the counter to be fully tested in n+1 iterations. The counter value output and the variable increment rate input are decoupled from the counter when the counter is not being tested. The counter is provided with a parallel load input to allow simultaneous resetting of each bit. Intermediate counter values may be checked to provide a means for localizing errors within the counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.