Transistor circuit
US4992755A · kind A · utility
20Cited by
1References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1990 |
| Grant date | Feb 12, 1991 |
| Priority date | — |
| Expiry date | Jan 19, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45394
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transistor circuit comprising a first differential amplifier which is composed of a differential pair and a current mirror. The transistor circuit further comprises a second differential amplifier which measures a differential offset voltage in the first differential amplifier and reduces this offset voltage by means of common mode current feedback. The transistor circuit thus provides a stable amplifier having a high speed and a low offset voltage which can be used advantageously in a logic output buffer so that, for example, an ECL output buffer can be realized in CMOS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.