Drive circuit for a power transistor
US4992924A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 1989 |
| Grant date | Feb 12, 1991 |
| Priority date | — |
| Expiry date | Nov 22, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/04126
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A power switching circuit (T115, T5) including at least one bipolar transistor stage (T5) and a control circuit for that stage, the control circuit including first bias means for applying forward bias to that stage during first time intervals (t3), and second bias means for applying reverse bias to that stage during second time intervals (t2, t4), the reverse bias being intended to prevent charge accumulating in the transistor while it is subjected to a reverse voltage. The first bias means comprise a first capacitor (C108) and a first switching circuit (D120, T113) serving, outside the first time intervals, for selectively charging the first capacitor by means of a DC voltage soruce, and for discharging the first capacitor into a control input (T115-G) of that stage; and the second bias means comprise a second capacitor (C107) and a second switching circuit (D119, D123, T113, T114) serving, outside the second time intervals, for selectively charging the second capacitor from the voltage supply, and for discharging the second capacitor into the control input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.