Reduced instruction set computing apparatus and methods
US4992934A · kind A · utility
146Cited by
13References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1990 |
| Grant date | Feb 12, 1991 |
| Priority date | — |
| Expiry date | Mar 30, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reduced instruction set computer (RISC) with a Harvard architecture is disclosed. The RISC may be designed to be used simply as a RISC or may be designed to be used to emulate a complex instruction set computer (CISC). Or, it may be designed for use as either. A CISC design methodology is disclosed whereby a RISC is designed and fabricated and whereby RISC emulation code is written concurrently with design and fabrication and also subsequent to fabrication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.