Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers
US4992938A · kind A · utility
177Cited by
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5Claims
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Key dates
| Filing date | Apr 23, 1990 |
| Grant date | Feb 12, 1991 |
| Priority date | — |
| Expiry date | Apr 23, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/384
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating point instruction control mechanism which processes loads and stores in parallel with arithmetic instructions. This results from register renaming, which removes output dependencies in the instruction control mechanism and allows computations aliased to the same register to proceed in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.