Cache memory device constituting a memory device used in a computer
US4992977A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 1988 |
| Grant date | Feb 12, 1991 |
| Priority date | — |
| Expiry date | Mar 25, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory device comprises a data cache memory, an instruction cache memory, an instruction code area change detector, and an instruction code change processor. The instruction code area change detector decides whether writing access to the data cache memory by the processor is to a data area or to an instruction area of a main memory. The instruction code change processor passes the data cache memory to perform direct writing into the main memory when the writing access is to the instruction area, and, when data for a processor address is cached in a tag section of the instruction cache memory, invalidates the effective flag of the tag section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.