Memory module utilizing partially defective memory chips
US4992984A · kind A · utility
36Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1989 |
| Grant date | Feb 12, 1991 |
| Priority date | — |
| Expiry date | Dec 28, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device which includes several partially defective memory chips and a control circuit for receiving an address signal corresponding to a storage cell address of each of the partially defective memory chips, and for controlling, in response to the address signal, the partially defective memory chips such that only one thereof is enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.