NMOS transistor having inversion layer source/drain contacts
US4994869A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1989 |
| Grant date | Feb 19, 1991 |
| Priority date | — |
| Expiry date | Jun 30, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
Abstract
A transistor (42) is provided having a gate conductor (44) formed adjacent a semiconductor substrate (46) and separated therefrom by a gate insulator (48). Sidewall spacers (52, 54) are formed at the sides of gate conductor (44) and adjacent semiconductor substrate (46). Diffused regions (56, 58) are formed within semiconductor substrate (46) in order to provide source/drain regions for transistor (42). Positive charges from radiation are trapped within sidewall spacers (52, 54) thereby attracting negative charges from semiconductor substrate (46) such that a negative charge layer is created between diffused region (56) and gate edge (50a) and also between diffused region (58) and gate edge (50b).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.